180nm CMOS 4x4 Bit Array Multiplier Design

Posted on 2023-06-04 Edited on 2024-09-07 Views: Word count in article: 32 Reading time ≈ 1 mins.

Project for course SME306 Advanced Digital CMOS IC Design in Spring 2023 semester. We designed and simulated a 180nm process 4x4 bit array multiplier using Cadence. The layout is displayed below.